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PJQA5V6 QUAD TVS/ZENER ARRAY FOR ESD AND LATCH-UP PROTECTION This Quad TVS/Zener Array family have been designed to Protect Sensitive Equipment against ESD and to prevent Latch-Up events in CMOS circuitry operating in the 3.0Vdc. This TVS array offers an integrated solution to protect up to 4 data lines where the board space is a premium. PRELIMINARY SPECIFICATION FEATURES 150W (8/20s), 24W (10/1000s) Power Dissipation Low Leakage Current, Maximum of 2A at rated voltage Very Low Clamping Voltage IEC61000-4-2 ESD 20kV air, 15kV Contact Compliance Industry Standard Surface Mount Package SOT23-6L 100% Tin Matte Finish (RoHS Compliance) 6 5 1 4 APPLICATIONS Personal Digital Assistant (PDA) SIM Card Port Protection (Mobile Phone) Portable Instrumentation Mobile Phones and Accessories Memory Card Port Protection 1 2 3 SOT23-6L MAXIMUM RATINGS (Per Device) Rating Peak Pulse Power (8/20s Waveform) ESD Voltage (HBM) Operating Temperature Range Storage Temperature Range Symbol P pp V ESD TJ Tstg Value 150 25 -55 to +150 -55 to +150 Units W kV C C ELECTRICAL CHARACTERISTICS (Per Device) Tj = 25C Parameter Reverse Stand-Off Voltage Reverse Breakdown Voltage Reverse Leakage Current Clamping Voltage (8/20s) Clamping Voltage (8/20s) Off State Junction Capacitance Off State Junction Capacitance Symbol VWRM VBR IR Vc Vc Cj Cj I BR = 1 mA VR = 3.0V I pp = 5 Amps I pp = 10 Amps 0 Vdc Bias f = 1MHz Between I/O pins and pin 2,5 3 Vdc Bias f = 1MHz Between I/O pins and pin 2,5 Conditions Min Typical Max 3.0 Units V V A V V pF pF 5.3 5.6 5.88 2 8 9.5 250 160 3/28/2006 Page 1 www.panjit.com PJQA5V6 TYPICAL APPLICATION EXAMPLE AND PACKAGE DIMENSIONS PRELIMINARY 3/28/2006 Data Line 1 Data Line 2 Data Line 3 Data Line 4 PJSMSxx Ground (Pins 2 and 5) Page 4 www.panjit.com |
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